Conventional approaches to framing high speed data streams, such as SMPTE (Society of Motion Picture and Television Engineers) 259M data streams, include providing a 30-input comparator that scans the decoded and descrambled data stream for a timing reference symbol (TRS) often represented as a sequence 3FFh, 000h, 000h. When the comparator detects a match of all of the thirty bits, it resets a modulo-10 counter. This counter is used to mark the start and end points of the receive characters, and is also used to generate a character-rate output clock that may be provided synchronously to the output characters.
FIG. 1 illustrates a circuit 10 illustrating such a conventional approach. The circuit 10 generally shows a descrambled bit stream presented to a 30-bit AND gate 12 through a 30-bit shift register 13. The circuit 10 also comprises a MOD5 counter 14, a 10-bit register 16, an AND gate 18 and a toggle flip-flop 20. Additional circuits receiving the character clock (i.e., the output of the toggle flip-flop 20) of the circuit 10 may encounter problems associated with creating a "phase-hop". "Phase-hop" generally occurs when the high or low phase of the output clock is reduced in size from its nominal width (i.e., a clock sliver), and also includes those cases where either (or both) of the high or low phase of the output clock is lengthened from its nominal width (i.e., a clock stretch). In a broadcast quality television system where video is a continuous bit-stream, this phase-hop may effect the output in a noticeable manner such as a visible distortion in the video signal.